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CY7C1325
256K x 18 Synchronous 3.3V Cache RAM
Features
* Supports 117-MHz microprocessor cache systems with zero wait states * 256K by 18 common I/O * Fast clock-to-output times -- 7.5 ns (117-MHz version) * Two-bit wrap-around counter supporting either interleaved or linear burst sequence * Separate processor and controller address strobes provides direct interface with the processor and external cache controller * Synchronous self-timed write * Asynchronous output enable * I/Os capable of 2.5-3.3V operation * JEDEC-standard pinout * 100-pin TQFP packaging * ZZ "sleep" mode
Functional Description
The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1325 allows both an interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the Cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control.
Logic Block Diagram
CLK ADV ADSC ADSP A[17:0] GW BWE BW 1
MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D 16 18
18
16
256K X 18 MEMORY ARRAY
D
Q DQ[15:8] BYTEWRITE REGISTERS Q DQ[7:0] BYTEWRITE REGISTERS
D BW 0 CE1 CE2 CE3
D ENABLE Q CE REGISTER CLK 18 18
INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[15:0] DP[1:0]
Selection Guide
7C1325-117 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
7C1325-100 8.0 325 10.0
7C1325-80 8.5 300 10.0
7C1325-50 11.0 250 10.0
7.5 350 10.0
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 May 10, 2000
CY7C1325
Pin Configurations
100-Lead TQFP
OE ADSC BWS 1 BWS 0 ADSP ADV 84 83 BWE
CE1
CE2
CE3
VDD
CLK
VSS
GW
NC
NC
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC NC NC VDDQ VSS NC NC DQ8 DQ9 VSS VDDQ DQ10 DQ11 NC VDD NC VSS DQ12 DQ13 VDDQ VSS DQ14 DQ15 DP1 NC VSS VDDQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
81
A9
80 79 78 77 76 75 74 73 72 71 70 69 68
A10 NC NC VDDQ VSS NC DP0 DQ7 DQ6 VSS VDDQ DQ5 DQ4 VSS NC VDD ZZ DQ3 DQ2 VDDQ VSS DQ1 DQ0 NC NC VSS VDDQ NC NC NC
CY7C1325
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
BYTE0
BYTE1
MODE A5
DNU DNU A11 A12
DNU DNU
V SS
2
VDD
A15 A16
A13
A14
A17
A4
A3
A2
A1
A0
CY7C1325
Pin Descriptions
Pin Number 85 Name ADSC I/O InputSynchronous InputSynchronous Description Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. A1, A0 address inputs, These inputs feed the on-chip burst counter as the LSBs as well as being used to access a particular memory location in the memory array. Address Inputs used in conjunction with A[1:0] to select one of the 256K address locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active LOW. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BWS 0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1. See Write Cycle Descriptions table for further details. Advance input used to advance the on-chip address counter. When LOW the internal burst counter is advanced in a burst sequence. The burst sequence is selected using the MODE input. Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct a global write, independent of the state of BWE and BWS[1:0]. Global writes override byte writes. Clock input. Used to capture all synchronous inputs to the device. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
84
ADSP
36, 37 50-44, 80-82, 99, 100, 32-35 94, 93
A[1:0] A[17:2]
InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputSynchronous Input-Clock InputSynchronous InputSynchronous InputSynchronous
BWS[1:0]
83
ADV
87 88
BWE GW
89 98 97 92 86
CLK CE1 CE2 CE3 OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. InputSnooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-powAsynchronous er standby mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving ZZ floating or NC will default the device into an active state. ZZ has an internal pull down. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal pull up. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are automatically three-stated when a WRITE cycle is detected. Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above. These signals can be used as parity bits for bytes 0 and 1 respectively. Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
64
ZZ
31
MODE
23, 22, 19, 18, 13, 12, 9, 8, 73, 72, 69, 68, 63, 62, 59, 58
DQ[15:0]
I/OSynchronous
74, 24 15, 41, 65, 91
DP[1:0] VDD
I/OSynchronous Power Supply
3
CY7C1325
Pin Descriptions (continued)
Pin Number 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1-3, 6, 7, 14, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95-96 38, 39, 42, 43 Name VSS I/O Ground Description Ground for the device. Should be connected to ground of the system.
VDDQ
I/O Power Supply -
Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.
NC
No connects.
DNU
-
Do not use pins. Should be left unconnected or tied LOW. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE 2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BWS[1:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWS0 controls DQ [7:0] and DP0 while BWS1 controls DQ [15:8] and DP1. All I/Os are three-stated during a byte write. Since these are common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ [15:0] and DP[1:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWS[1:0]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register, burst counter/control logic and delivered to the RAM core. The information presented to DQ[15:0] and DP[1:0] will be written into the specified address location. Byte writes are allowed, with BWS0 controlling DQ[7:0] and DP0 while BWS1 controlling DQ [15:8] and DP1. All I/Os are three-stated when a write is detected, even a byte write. Since these are common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[15:0] and DP[1:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE.
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 7.5 ns (117-MHz device). The CY7C1325 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWS[1:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE 2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
4
CY7C1325
Burst Sequences
This family of devices provide a 2-bit wrap-around burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Table 1. Counter Implementation for the Intel(R) Pentium(R)/80486 Processor's Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 Table 2. Counter Implementation for a Linear Sequence First Address AX + 1, Ax 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10
5
CY7C1325
Cycle Description Table[1, 2, 3]
Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADD Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L X X L L L L L X X H H X H X X H H X H CE3 X X H X X X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WE X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Notes: 1. X="Don't Care," 1=Logic HIGH, 0=Logic LOW. 2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[1:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a "don't care" for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
6
CY7C1325
Write Cycle Descriptions[1,2,3,4]
Function Read Read Write Byte 0 - DQ[7:0] and DP 0 Write Byte 1 - DQ[15:8] and DP1 Write All Bytes Write All Bytes GW 1 1 1 1 1 0 BWE 1 0 0 0 0 X BWS1 X 1 1 0 0 X BWS 0 X 1 0 1 0 X
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V 2tCYC Min. Max. 10 2tCYC Unit mA ns ns
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage on VDD Relative to GND................ -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[5] ...............................................-0.5V to VDD + 0.5V
DC Input Voltage[5]........................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Com'l Ambient Temperature[6] 0C to +70C VDD 3.135V to 3.6V VDDQ 2.375V to VDD
Notes: 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 6. TA is the case temperature.
7
CY7C1325
Electrical Characteristics Over the Operating Range
7C1325 Parameter VOH VOL VIH VIH VIL VIL IX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input HIGH Voltage Input LOW Voltage[5] Input LOW Voltage
[5]
Test Conditions VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -2.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V, VDDQ = 2.5V GND VI VDDQ Input = VSS Input = VDDQ Input = VSS Input = VDDQ GND VI VDD, Output Disabled
[7]
Min. 2.4 2.0
Max.
Unit V V
0.4 0.7 2.0 1.7 -0.3 -0.3 -1 -30 5 -5 30 -5 5 -300 350 325 300 250 125 110 100 90 10 VDD + 0.3V VDD + 0.3V 0.8 0.7 1
V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA mA
Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ
IOZ IOS IDD
Output Leakage Current Output Short Circuit Current VDD Operating Supply Current
VDD = Max., VOUT = GND VDD = Max., Iout = 0 mA, f = fMAX= 1/tCYC 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 11-ns cycle, 90 MHz 20-ns cycle,50 MHz
ISB1
Automatic CE Power-Down Current--TTL Inputs
Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching
8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 11-ns cycle, 90 MHz 20-ns cycle,50 MHz
ISB2
Automatic CE Power-Down Current -- CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs
Max. VDD, Device Deselected, VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static
All speeds
ISB3
8.5-ns cycle, 117 MHz Max. VDD, Device Deselected, VIN VDDQ - 0.3V or VIN 0.3V, 10-ns cycle, 100 MHz f = fMAX, inputs switching 11-ns cycle, 90 MHz 20-ns cycle,50 MHz
95 85 75 65 30
mA mA mA mA mA
ISB4
All speeds Automatic CE Power-Down Current Max. VDD, Device Deselected, -- TTL Inputs VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static
Capacitance[8]
Parameter CIN CI/O Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 5.0V Max. 4 4 Unit pF pF
Notes: 7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 8. Tested initially and after any design or process changes that may affect these parameters
8
CY7C1325
AC Test Loads and Waveforms
R1 OUTPUT Z0 =50 RL =50 5 pF VL =1.5V INCLUDING JIGAND SCOPE R2 GND 2.5 ns
[9]
2.5V OUTPUT ALL INPUT PULSES 2.5V 10% 90% 90% 10% 2.5 ns
(a)
(b)
1325-3 1325-4
Switching Characteristics Over the Operating Range[10]
-117 Parameter tCYC tCH tCL tAS tAH tCDV tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise BWS[1:0], GW, BWE Set-Up Before CLK Rise BWS[1:0], GW, BWE Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Enable Set-Up Chip Enable Hold After CLK Rise Clock to High-Z Clock to Low-Z
[11, 12] [11, 12]
-100 Min. 10 4.0 4.0 2.0 0.5 Max. 11 4.5 4.5 2.0 0.5 8.0 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 0 3.5 0 0 3.5
-90 Min. Max. 20 4.5 4.5 2.0 0.5 8.5 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 3.5 0 3.5
-50 Min. Max. Unit ns ns ns ns ns 11.0 ns ns ns ns ns ns ns ns ns ns ns ns 3.5 3.5 3.5 ns ns ns ns ns
Description Clock Cycle Time
Min. 8.5 3.0 3.0 2.0 0.5
Max.
7.5 2.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 3.5 0 3.5
OE HIGH to Output High-Z[11, 13] OE LOW to Output Low-Z OE LOW to Output Valid
[11, 13]
Notes: 9. R1=1667 and R2=1538 for IOH/IOL=-4/8 mA, R1=521 and R2=481 for IOH/IOL=-2/2 mA. 10. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. 11. tCHZ, tCLZ, tEOHZ, and t EOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 12. At any given voltage and temperature, t CHZ (max) is less than tCLZ (min). 13. This parameter is sampled and not 100% tested.
9
CY7C1325
Timing Diagrams
Write Cycle Timing [14, 15]
Single Write tCH tCYC
Burst Write
Pipelined Write Unselected
CLK
tADH tADS tCL ADSP ignored with CE1 inactive
ADSP
tADS tADH
ADSC initiated write
ADSC
tADVS tADVH
ADV
tAS
ADV Must Be Inactive for ADSP Write
WD1 tAH WD2 WD3
ADD
GW
tWS tWH tWS CE1 masks ADSP tWH
WE
tCES tCEH
CE1
tCES tCEH Unselected with CE2
CE2
CE3
tCES tCEH
OE
tDS
tDH High-Z
Data In
High-Z
1a 1a
2a = UNDEFINED
2b
2c
2d
3a
= DON'T CARE
Notes: 14. WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table). 15. WDx stands for Write Data to Address X.
10
CY7C1325
Timing Diagrams (continued)
Read Cycle Timing[14, 16]
Single Read tCYC
Burst Read tCH Unselected Pipelined Read
CLK
tADS tADH tCL ADSP ignored with CE1 inactive
ADSP
tADS ADSC initiated read
ADSC
tADVS tADH tADVH RD1 tAH RD2 RD3 Suspend Burst
ADV
tAS
ADD
GW
tWS
tWH
tWS
WE
tCES tCEH tWH CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES tCEH
CE3
tCES tCEH tEOV tCDV tOEHZ 2a tCLZ tCHZ = DON'T CARE = UNDEFINED
OE
tDOH 2b 2c 2c 2d 3a
Data Out
1a 1a
Note: 16. RDx stands for Read Data from Address X.
11
CY7C1325
Timing Diagrams (continued)
Read/Write Cycle Timing
tCH
tCYC
tCL
CLK
tAH
B C D
tAS
ADD
A
tADS
tADH
ADSP
tADS tADH
ADSC
tADVS tADVH
ADV
tCES tCEH
CE1
tCES tCEH
CE
tWES tWEH
WE
ADSP ignored with CE1 HIGH tEOHZ
Q(A) Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D)
OE
tCLZ
Data In/Out
tCDV
tDOH tCHZ
Device originally deselected
WE is the combination of BWE, BWS [1:0], and GW to define a write cycle (see Write Cycle Descriptions table). CE is the combination of CE 2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
12
CY7C1325
Timing Diagrams (continued)
Pipeline Timing tCH tCYC tCL
CLK
tAS
ADD
A
B
C
D
E
F
G
H
tADS
tADH
ADSP
ADSC
ADV
tCES tCEH
CE1
CE
tWES tWEH
WE
ADSP ignored with CE1 HIGH
OE
tCLZ
Data
Q(A) Q(B) Q(C) Q(D)
D (E)
D (F)
D (G)
D (H) D(C)
tCDV tDOH tCHZ
Device originally deselected
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON'T CARE = UNDEFINED
13
CY7C1325
Timing Diagrams (continued)
OE Switching Waveforms
OE
tEOHZ tEOV
I/Os
three-state
tEOLZ
14
CY7C1325
Timing Diagrams (continued)
ZZ Mode Timing [17, 18]
CLK
ADSP
HIGH
ADSC CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
ICC
ICC(active) ICCZZ
tZZREC
I/Os Three-state
Notes: 17. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 18. I/Os are in three-state when exiting ZZ sleep mode.
15
CY7C1325
Ordering Information
Speed (MHz) 117 100 80 50 Ordering Code CY7C1325-117AC CY7C1325-100AC CY7C1325-80AC CY7C1325-50AC Package Name A101 A101 A101 A101 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack Operating Range Commercial
Document #: 38-00652-B
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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